In the rapidly advancing semiconductor manufacturing industry, complementary metal oxide semiconductor (CMOS) FinFET devices are favored for many logic and other applications. Thus FinFET devices are integrated into various types of semiconductor devices currently being manufactured. FinFET devices typically include a plurality of fin-shaped oxide diffused (OD) regions with high aspect ratios formed vertically with respect to a top surface of the substrate, wherein the fin-shaped OD regions define the active areas in which channel and source/drain regions of the CMOS transistor devices are formed. Typically, the fin-shaped OD regions are isolated, raised three-dimensional (3D) structures. Gates of the CMOS FinFET devices are formed over and along the sides of the fins, utilizing the advantage of an increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Polycrystalline silicon (POLY) lines are used for carrying control signals to the gates of the CMOS transistors wherein the gates may also be made of POLY in some embodiments.
A cell grid is a cell structure that implements various CMOS transistors in a circuit with the fin-shaped OD regions and the POLY lines running in orthogonal directions on separate layers formed on a semiconductor substrate. The height of the cell grid is optimally chosen for the circuit during circuit design while the width of the cell grid is determined by the number of CMOS devices implemented in the cell grid. The larger the number of CMOS devices implemented, the larger the width and thus the area of the cell grid.